One bit Comparator VHDL code using Behavioral

One bit Comparator VHDL code using Behavioral  

A comparator is a digital circuit or a device that compares two values and gives the output in the form of comparison of both these values. There are three outputs and at a time only one of these will become high. Each of these correspond to the result of the comparison, i.e. whether A>B, A<B or A=B.

Given below is a behavioral approach of writing the code for a 1 bit comparator.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity comparator  is

PORT    ( a,b,en : in std_logic;

               gr,ls,eq : out std_logic);

end comparator;

Architecture behavioral of comparator is

Begin

process(a,b,sel)

begin

        if(sel ='1') then

                

              if (a>b) then

                   gr<='1';

              

             elsif (b>a) then

                   ls<='1';

            

               else

                   eq<='1';

           

               end if;

           

       else

      end if;

end Process;

end behavioral;

The code above is easy to understand and there are only basic statements involved along with assignments. The process block is used as it makes it simple to construct and grasp. Also, there is nesting of IF statements as we used in C.

We could have used the datatype BIT for simplicity but it is normally avoided due to the fact that when dealing with vectors, the operations become incompatible between more than one datatype so we focus all programs on the core datatype of STD_LOGIC and its vector only.