Sequential statements in VHDL

Sequential statements in VHDL

Before talking about sequential statements and their importance in VHDL coding, lets just come to the terms of where you stand in your understanding of vhdl basics.

As long as you are familiar with the VHDL Process, it really gets easy from there on. Its like knowing the job but the tools required are still unknown. 

Simply writing a process and declaring variables doesn't help our cause; we need effective statements that we can use inside a process and make a program work. Such statements are written in a definite sequence and are processed in VHDL is the same manner.

Some important sequential statements of VHDL that we need to know about that we use inside Processes commonly are:

• IF ELSE statement
• CASE Statement
• Looping Statements

Most of the problems are solved by the IF ELSE set of statements in VHDL but sometimes it simply becomes too hectic and messy writing so many conditions using it. In those cases where the conditions are simply too many, we use CASE statement in VHDL to simplify the work. It also makes debugging of a program easy.

Lets look at the 4:1 MUX that we designed using concurrent statements again  and see how will we go on writing code for its working using IF ELSE statement.

Architecture behave of mux is

Begin

Process(S,A,B,C,D)

variable temp : std_logic;            // variable declaration

Begin

if(S="00")then

temp:=A;

elsif(S="01")then                   // note that it is 'elsif' not 'else if' of C

temp:=B;

elsif(S="10")then

temp:=C;

else

temp:=D;

end if;                                 // used to terminate the if statement

OUT=temp;                        // passing on the value of the variable

end Process;

end behave; 

Here, we declared a variable and in each case we assigned the final value to it instead of directly assigning it to the output signal. This comes in handy when we have feedback loops where the output of one is the input of the other. Practicing with variables also solves many issues that might  arise related to assignment or re-usability.

Also, note the sensitivity list of the process here includes all the input signals because a change in either of the  four values will directly affect the output of the system.

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The case statement is usually used for a large number of conditions and it is similar to the 'Switch' statement of C (without being sequential in nature of course).

The program above can be written using CASE as follows:

Process(S,A,B,C,D)

variable temp:std_logic;

Begin

case S is

when "00" => temp:=A;

when "01"  =>temp:=B;

when "10"  =>temp:=C;

when Others =>temp:=D;

end case;

OUT=temp;

end Process;

The CASE statement works in different situations or cases and assigns a specific value to the output in each such case as is clear from the code.

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Looping Sequential Statements in VHDL are completely different from the above two specified statements. It simplifies our programs in cases when there are vectors involved or where there are large number of assignments of signals or variables.

These are the same as used in C but only the syntax varies as shown in the snippets below. Let us see how to use for loop in VHDL.

FOR loop in VHDL:

for i in 0 to 4 loop

a(i)=b(i);

end loop;

WHILE loop in VHDL :

while (i<5)

a(i)=b(i);

end loop;

Mostly, the FOR loops are preferred for their simplicity and WHILE loops are used only for waiting for some condition to be satisfied in a VHDL code. The for loop as well the while loop are used to perform the same function in VHDL as in C or C++ or any other coding language.

All these statements are called sequential statements and are commonly used in all the programs as they are the basic building tools in a  programmer's hands.