Factorial using Verilog code

Factorial of Number using Verilog 

In order to determine the factorial of any number, here we take input as 3-bit and output as 32-bit, output is taken as reg. Now, always block is defined with respect to input. Whenever input is given factorial become one. An integer I is also initialized as 0, while i is less than the input, the loop starts and there is always an increment in value of i and factorial become equal to the multiplication of fact and the current value of i. $display is used to display the value of factorial of the given number, and the hence factorial is displayed.

Verilog code for Factorial of any Number:

module factorial(fact,n);
output [31:0]fact;
input [2:0]n;
reg [31:0]fact;
integer i;
always@(n)
begin
fact=1;
i=0;
while(i<n)
begin
i=i+1;
fact=i*fact;
$display("fact =%d",fact);
end
end
endmodule 

OUTPUT: