Traffic light controller using verilog code
TRAFFIC LIGHT CONTROLLER
INTRODUCTION
Traffic signals
are used to control the flow of vehicles. In the recent years, the need of
transportation has gain immense importance for logistics as well as for common
human. This has given rise to the number of vehicles on the road. Due to this
reason, traffic jams and road accidents are common sides in any city.Traffic
signal provide an easy, cheap, automatic and justified solution to the road
points where the vehicles may turn to other direction.
Control systems
are:
Red for Stop,
Yellow for Wait,
Green For Go.
Source code
`define TRUE 1'b1
`define FALSE 1'b0
`define RED 2'd0
`define YELLOW 2'd1
`define GREEN 2'd2
`define S0 3'd0
`define S1 3'd1
`define S2 3'd2
`define S3 3'd3
`define S4 3'd4
`define S5 3'd5
`define S6 3'd6
`define S7 3'd7
`define Y2RDELAY 3
module
redsignal(east,west,south,north,a,clk,clear,b,c,d);
output reg [1:0]east,west,north,south;
input a,b,c,d;
input clk,clear;
reg [2:0]state;
reg [2:0]next_state;
initial
begin
state=`S0;
next_state=`S0;
west=`GREEN;
east=`RED;
north=`RED;
south=`RED;
end
always @(posedge clk)
state=next_state;
always @(state)
begin
case(state)
`S0:begin
west=`GREEN;
east=`RED;
north=`RED;
south=`RED;
end
`S1:begin
west=`YELLOW;
east=`RED;
north=`RED;
south=`RED;
end
`S2:begin
west=`RED;
east=`RED;
north=`GREEN;
south=`RED;
end
`S3:begin
west=`RED;
east=`RED;
north=`YELLOW;
south=`RED;
end
`S4:begin
west=`RED;
east=`GREEN;
north=`RED;
south=`RED;
end
`S5:begin
west=`RED;
east=`YELLOW;
north=`RED;
south=`RED;
end
`S6:begin
west=`RED;
east=`RED;
north=`RED;
south=`GREEN;
end
`S7:begin
west=`RED;
east=`RED;
north=`RED;
south=`YELLOW;
end
endcase
end
always @(state or clear or a or b or c or
d)
begin
if(clear)
next_state=`S0;
else
case(state)
`S0:if(a)
next_state=`S0;
else
next_state=`S1;
`S1:begin
repeat(`Y2RDELAY) @(posedge clk);
next_state=`S2;
end
`S2:if(b)
next_state=`S2;
else
next_state=`S3;
`S3:begin
repeat(`Y2RDELAY) @(posedge clk);
next_state=`S4;
end
`S4:if(c)
next_state=`S4;
else
next_state=`S5;
`S5:begin
repeat(`Y2RDELAY) @(posedge clk);
next_state=`S6;
end
`S6:if(d)
next_state=`S6;
else
next_state=`S7;
`S7:begin
repeat(`Y2RDELAY) @(posedge clk);
next_state=`S1;
end
default:next_state=`S0;
endcase
end
Endmodule
Output :-
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