Universal shift Register using VHDL code

Universal shift Register using VHDL code

Universal shift Register

Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift register along with parallel load provision is referred to as universal shift register. Such a shift register capable of storing n input bits .

 4-bit universal shifter

library ieee;

use ieee.std_logic_1164.all;

entity uni_shift is

port ( clk,reset,sir,sil : in std_logic;

                   s     : in std_logic_vector(1 downto 0);

                  pin    : in std_logic_vector(3 downto 0);

              q ,qbar    : inout std_logic_vector(3 downto 0));

end uni_shift;

architecture behaviour of uni_shift is

component mux is

port ( i0,i1,i2,i3 : in std_logic;

              s   : in std_logic_vector(1 downto 0);

              y    : out std_logic);

end component;

component dff_asy is

port ( d,clk,reset : in std_logic;

              q,qbar   : out std_logic);

end component;

signal y : std_logic_vector(3 downto 0):="0000" ;

begin

mux1 : mux port map (q(3),sir,q(2),pin(3),s,y(3));

mux2 : mux port map (q(2),q(3),q(1),pin(2),s,y(2));

mux3 : mux port map (q(1),q(2),q(0),pin(1),s,y(1));

mux4 : mux port map (q(0),q(1),sil,pin(0),s,y(0));

ff1  : dff_asy port map (y(3),clk,reset,q(3),qbar(3));

ff2  : dff_asy port map (y(2),clk,reset,q(2),qbar(2));

ff3  : dff_asy port map (y(1),clk,reset,q(1),qbar(1));

ff4  : dff_asy port map (y(0),clk,reset,q(0),qbar(0));

end behaviour;

OUTPUT