4-bit Synchronous Counter wihout Reset using Verilog
Digital counters count upwards from zero to some pre-determined count value on the application of a clock signal. In this logic, the counter counts the clock pulses without reset, we take output as 4-bit. We initialised count as 0 and always at the positive edge of clock count gets incremented by one.
Verilog code for 4 bit Synchronous Counter wihout Reset:
module withoutreset4bit_syn_counter(count,clk);
input clk;
wire clk;
output count;
reg[3:0] count;
initial count=4'b0000;
always@(posedge clk)
begin
count<=count+1;
end
endmodule
OUTPUT:
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