Digital clock using verilog codes
DIGITAL CLOCK
A digital clock is a type of clock that displays the time digitally (i.e. in numerals or other symbols), as opposed to an analog clock, where the time is indicated by the positions of rotating hands digital clocks are often associated with electronic drives, but the "digital" description refers only to the display, not to the drive mechanism. (Both analog and digital clock. The first digital pocket watch was the invention of Austrian engineer Josef Pallweber who created his "jump-hour" mechanism in 1883.
Uses
of digital clocks:
Digital
clocks can be very small and inexpensive devices that enhance the popularity of
product designs, they are often incorporated into all kinds of devices such as
cars, radios, televisions, microwave
ovens,
standard ovens, computers and cell phones.
Example:
SOURCE
CODE:
module
clock(out,reset,clk,seg,enable,hours,stopwatch);
input
reset,clk,stopwatch;//reset,clk and stopwatch is the input of digital clock.
output
reg [7:0]out;//out is a 8 bit output,which is used for LED.
output
reg [3:0]enable,seg;//4 bit enable and segment signal are used.
reg
[25:0]count1,count2;//count1 and count2 is used for count the posedge of clock.
reg
[3:0]sec0,sec1,min0,min1;//sec0,sec1,min0,min1 are 4 bit counters.
reg
clk_1s,clk_count ;//clk_1s will goes high in every 1 second and clk_count is
used for switching.
reg
[3:0]counter;//4 bit counter is used.
output
reg [4:0]hours;//5 bit binary output is used for hours.
always
@(posedge clk)
begin
if(reset)
count1=26'd0;
else
if
(count1
== 26'd25000000)//this always block is used for generating clock of 1 second.
begin
clk_1s = ~clk_1s;
count1
= 26'd0; end
else
if(stopwatch==1'b1)//if stopwatch is high then our output will stop.
clk_1s=1'b0;
else
count1
= count1+26'd1;
end
always@(posedge
clk)
begin
if(count2==26'd10000)//this
always block is used for switching the 7 segment LED.
begin
clk_count=~clk_count;
count2<=26'd0;
end
else
count2<=count2+1;
end
always@(posedge
clk_1s )
begin
if(reset==1'b1)
begin //this always block works on 1 second of clock.
sec0=0;
sec1=0;
min0=0;
min1=0;
end
else
if(sec0<9)//if LSB bit of second is less than 9 then it will increse.
sec0=sec0+1;
else
if(sec1<5) //if MSB bit of second is less than 5 then it will increse
begin //and LSB bit of second will become
0.
sec1=sec1+1;
sec0=0;
end
else
if(min0<9) //if LSB bit of minute is less than 9 then it will increse
begin //and LSB bit of second will become
0.
min0=min0+1; //and MSB bit of second will become 0.
sec0=0;
sec1=0;
end
else
if(min1<5)//if MSB bit of minute is less than 5 then it will increse
begin //and MSB bit of second will become 0.
min1=min1+1;
//and LSB bit of second will become 0.
sec0=0; //and LSB bit of minute will become 0.
sec1=0;
min0=0;
end
else
if(min1==4'd5&&min0==4'd9&&sec0==4'd9&&sec1==4'd5)
begin //if minute is 59 and second is 59 then it
will work.
sec0=0; //if all the above conditions are satisfied
then
sec1=0;
// all the minutes and seconds will become 0
min0=0;//
and hours will incremented and give binary output.
min1=0;
hours=hours+5'd1;
end
else
if(hours==5'd24)
begin
hours=5'b00000;//if
hours is greater than 24 then
sec0=0; //all the minutes,seconds and hours will
start from 0.
sec1=0;
min0=0;
min1=0;
end
end
always
@(posedge clk_count)//this always block is used for enabling the LED
begin //and assigning the value of
minute and second in seg
if(reset) //and enabling the dot on 7 segment
LED.
counter=0;
else
counter=counter+1;
case(counter)
4'b0001
:
begin enable=4'b1110;
seg <= sec0;
out[7]<=1; end
4'b0010
:
begin enable=4'b1101;
seg <= sec1;
out[7]<=1; end
4'b0011
:
begin enable=4'b1011;
seg <= min0;
out[7]<=clk_1s; end
4'b0100
:
begin enable=4'b0111;
seg <= min1;
out[7]<=1; end
default
: counter=4'b0000;
endcase
end
//this
always block is used as BCD to 7 segment converter.
always@(seg)
begin
case(seg)//this
case is working on seg.
4'b0000 :out[6:0] = 7'b0000001;
4'b0001 :out[6:0] = 7'b1001111;
4'b0010 :out[6:0] = 7'b0010010;
4'b0011 :out[6:0] = 7'b0000110;
4'b0100 :out[6:0] = 7'b1001100;
4'b0101 :out[6:0] = 7'b0100100;
4'b0110 :out[6:0] = 7'b0100000;
4'b0111 :out[6:0] = 7'b0001111;
4'b1000 :out[6:0] = 7'b0000000;
4'b1001 :out[6:0] = 7'b0000100;
endcase
end
endmodule
UCF
file:
Net "clk" LOC = "T9" ;
Net "reset" LOC = "M13" ;
Net "out[0]" LOC = "N16" ;
Net "out[1]" LOC = "F13" ;
Net "out[2]" LOC = "R16" ;
Net "out[3]" LOC = "P15" ;
Net "out[4]" LOC = "N15" ;
Net "out[5]" LOC = "G13" ;
Net "out[6]" LOC = "E14" ;
Net "out[7]" LOC = "P16" ;
Net "enable[0]" LOC = "D14" ;
Net "enable[1]" LOC = "G14" ;
Net "enable[2]" LOC = "F14" ;
Net "enable[3]" LOC = "E13" ;
Net "hours[0]" LOC = "K12" ;
Net "hours[1]" LOC = "P14" ;
Net "hours[2]" LOC = "L12" ;
Net "hours[3]" LOC = "N14" ;
Net "hours[4]" LOC = "P13" ;
Net "stopwatch" LOC = "K13" ;
Ø Advantages and
disadvantages:
1. They are simple in use.
2. Low cost or less
electronic equipment required.
3. Require graphic board with
digital output.
0 Comments